For my Ph.D., I have focused on digital machine learning accelerator design.

Machine learning algorithm development Theano, Matlab
System modeling & analysis System C, Vivado-HLS
RTL Design Verilog, VCS
Logic Synthesis, Placement, and Route Design Compiler, IC Compiler, SoC Encounter
Circuit level simulation Hspice, Hsim
FPGA implementation Virtex 5 with ISE, Virtext 7 with Vivado, Ultrascale with Vivado
Sign-off Analysis Primetime-PX
Script language Python, Perl, Tcl/tk, Ocean
Library Characterization Siliconsmart